Method of forming a semiconductor device

ABSTRACT

In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation between the clustered process chambers takes place in a controlled environment such as nitrogen or a vacuum. In some embodiments, the method provides an oxide layer to be used as part of the device, such as a tunnel oxide for a flash-EEPROM, or as a general gate oxide. Alternatively, the steps can be used to sculpt through oxidation various levels of a substrate, thereby allowing for embedded memory architecture. Cleaning between oxidation steps offers the advantage of providing a more defect-free oxide layer or providing access to a more defect-free level of substrate.

RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/133,132,filed Apr. 25, 2002; which is a divisional of application Ser. No.09/652,723, filed Aug. 31, 2000, now U.S. Pat. No. 6,589,877; which is adivisional of application Ser. No. 09/017,453, filed Feb. 2, 1998, nowU.S. Pat. No. 6,475,927.

TECHNICAL FIELD

The present invention relates to the formation of semiconductor devices.More particularly, the present invention relates to the formation of anoxide layer as part of a device or as used in the fabrication of thedevice.

BACKGROUND OF THE INVENTION

In the semiconductor industry, oxide films are used in a variety ofapplications. Oftentimes they are used for scratch protection andpassivation purposes. Oxide films are also used as a dielectric orinsulative layer, electrically separating various regions or structures.For example, an oxide film can be used as a dielectric between differentlevels of metal in a semiconductor device. Such a film could also beused for field isolation. Moreover, an oxide film can serve as a gateoxide, wherein the film is provided above an area, such as asemiconductor substrate, having a source region, a drain region, and aninterposing channel region. A gate, in turn, is formed on the oxidefilm. As a result, the voltage applied to the gate must reach aparticular threshold before overcoming the insulative effects of theoxide and allowing current to flow through the channel. When used asfield isolation, an oxide is formed in order to electrically insulateone device, such as a transistor, from another.

Whether for field isolation purposes or for application in the gatestack of a transistor, providing the oxide typically begins by exposingdesignated oxide regions of a substrate to an oxidizing ambient througha patterned mask. The mask may be made, for example, of silicon nitride.For purposes of explaining the current invention, it is assumed that thesubstrate represents the surface of a wafer and is comprised generallyof silicon. Nevertheless, this invention is understood to cover deviceshaving a substrate comprising any construction made of semiconductivematerial, including but not limited to bulk semiconductive materialssuch as a semiconductor wafer (either alone or in assemblies comprisingother materials thereon) and semiconductive material layers (eitheralone or in assemblies comprising other materials). Upon exposure to theoxidizing ambient, the unprotected portions of the silicon substrateoxidize into silicon dioxide (SiO₂). The silicon at and below thesurface of the substrate that oxidizes is often referred to as havingbeen “consumed.” It follows that the amount of silicon consumed canindicate the depth of SiO₂ beneath the substrate's original surface. Asa result, greater consumption allows for a greater depth of SiO₂ and,thus, greater electrical isolation between devices or between activeareas within a device.

The consuming effect of oxide films on silicon serves other purposes aswell. For example, greater consumption in a particular area of the waferallows access to a lower level of silicon within the substrate.Accordingly, removing the oxide results in a wafer topography havingdifferent elevations of silicon, depending upon the amount of prioroxidation in each area. This is particularly helpful in embedded dynamicrandom access memory (DRAM) processing, wherein the memory cell arrayshould be embedded deeper within the wafer than other memory elements.

Oxidizing the exposed substrate, as discussed above, is often referredto as “growing” the oxide. Oxides can be grown in a “dry” process usingoxygen (O₂) or in a “wet” process using steam as the oxidizing agent. Asan alternative to growing, oxides can be deposited on the substrate withtechniques such as sputter deposition or chemical vapor deposition(CVD).

Oxide layers have a large impact on device performance due to their rolein isolating active device regions and in establishing voltagethresholds for devices. Thus, there is always a need in the art for highquality oxide films. Further, as the dimensions of semiconductor devicesare scaled down to enhance circuit density and speed, the oxide filmsmust advance accordingly. Therefore, those skilled in the art areconstantly striving to provide oxide films that are thinner and thathave a high dielectric constant.

However, during the deposition or growth of oxides, defects in the oxidecan occur due to the presence of certain constituents within the layer,such as contaminants exposed to the oxide. For example, particulatematter in the process atmosphere is one source of contamination. Evenwhen the oxide or other layers are developed in a “clean room”environment, wherein filters and other techniques attempt to removeparticles from the environment, particles that are too small for thesetechniques to handle may nevertheless end up within the oxide layer.Further attempts at reducing defects have been made by clusteringtogether the chambers for several wafer processes in an environmentisolated from and even more controllable than the clean room atmosphere.Transferring the wafers between the clustered chambers can involve theuse of a wafer carrier capable of maintaining a vacuum or a nitrogenatmosphere. See, for example, U.S. Pat. No. 5,613,821 and U.S. Pat. No.5,344,365. Nonetheless, there is a constant need in the art for furtherlowering the number of defects in oxide films, including a need formethods of handling contaminants that find their way to the waferdespite the controlled environment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a process flow diagram of one exemplary embodiment of thepresent invention.

FIGS. 2 a through 2 e illustrates a prior art process for forming anembedded DRAM.

FIGS. 3 a through 3 c depicts a second exemplary embodiment of thecurrent invention.

FIGS. 4 a through 4 e demonstrates a third exemplary embodiment of thecurrent invention.

FIG. 5 shows a portion of a flash-electrically erasable programmableread only memory.

FIG. 6 illustrates an in-process semiconductor device that iselectrically isolated using a shallow trench isolation process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As seen in FIG. 1, at least one embodiment of the current inventioncomprises a cleaning stage 20, a stage involving forming an oxide (or anoxynitride) 22, and a stage of forming a structure 24. These basicstages, 20, 22, and 24, further comprise more detailed steps. Forexample, cleaning stage 20 includes a vapor clean 20 b. In many casesthis vapor clean 20 b is performed in at least five seconds and occursat a temperature ranging between 50° and 75° C. This vapor clean 20 bmay take the form of an ultraviolet-chlorine clean, wherein ultravioletlight excites and dissociates a gas containing chlorine. As a result,chlorine radicals are generated. These chlorine radicals act asgettering agents, penetrating the oxide layer and bonding withconstituents therein, such as contaminants. These radicals areparticularly useful in neutralizing the harm caused by metallicconstituents within an oxide layer. This ultraviolet-chlorine cleangenerally takes between ten and sixty seconds and may occur at pressuresless than, greater than, or equal to 760 torr. The temperature for thisprocess is generally between 50° and 150° C. but is preferably between60° and 80° C.

Alternatively, the vapor clean 20 b may comprise an HF vapor clean. Asone example of the parameters needed for an HF vapor clean, the pressureshould be 1 mtorr, the temperature should be less than 200° C., and theexposure to HF should last five to ten seconds. The pH can beestablished at any level between 1 and 10. Still other alternativesinclude using tetramethylammonium hydroxide (TMAH) in the vapor cleanprocess to assist in cleaning. For purposes of explaining the currentinvention, the TMAH is assumed to have a pH of 3, although one ofordinary skill in the art can appreciate that the pH level can varyaccording to the particular passivation requirements of a givenembodiment. Also for purposes of explanation, it is assumed that a waferis undergoing the methods of the current invention, although this is notrequired to practice the invention, as individual devices could also beprocessed. In general, the cleaning stage helps to remove residue frometches executed earlier in the device-formation process.

As a part of the cleaning stage 20, an optional wet clean 20 a may beperformed in addition to the vapor clean 20 b. Preferably, the wet clean20 a is performed before the vapor clean 20 b. This wet clean step 20 amay be an RCA clean, which involves cleaning solutions developed by RCA.These solutions employ hydrogen peroxide chemistry, the two most commonsolutions being “standard clean 1” (SC-1) and “standard clean 2” (SC-2).The solution SC-1 typically comprises ammonium hydroxide, hydrogenperoxide, and deionized water in the following volume ratio: 1 NH₄OH:1H₂O₂:5 H₂O. The solution SC-2 generally has the following composition: 6H₂O:1 H₂O₂:1 HCl. Typically wafers are immersed in the RCA cleaningsolutions for 10 minutes at 20° to 80° C. for each solution, withdeionized water rinses between immersions. There is also a finaldeionized water rinse after all immersions. The wet clean 20 a serves topassivate the wafer by allowing for a termination of the silicon surfacewith hydrogen atoms. In this way, a hydrophilic or a hydrophobic surfacecan be prepared.

Once the wafer surface has been cleaned, it is ready for oxide oroxynitride formation, as indicated by stage 22. In many embodiments,this stage 22 initially involves growing an oxide on the wafer surface22 c, which consumes the silicon down to a particular level within thesubstrate. However, the current invention includes embodiments whereinoxide is deposited 22 b at the initiation of this stage 22.

In at least one embodiment, oxide growth can be accomplished through arapid thermal oxidation (RTO) process 22 d at a temperature generallyranging from 800° to 1100° C. This RTO process 22 d is carried out untilit has produced an oxide thickness of at least generally 10 angstroms.

In addition to this initial step of growing an oxide, there areadditional steps which may take place to enhance the oxide formationstage 22. For instance, after the vapor clean 20 b has been performed,yet before the RTO process 22 d begins, it may be beneficial to inducechemical oxide growth on the wafer through an ultraviolet-ozonetreatment 22 a, wherein ultraviolet radiation is used to enhance theoxidation rate of the silicon substrate in an ozone environment. Thistreatment 22 a is preferably carried out long enough to provide ahigh-quality oxide layer having a thickness generally ranging from 10 to15 angstroms. Regardless of whether the oxide is provided in one step ora plurality of steps, it is preferable to have approximately 30 to 40angstroms of oxide once step 22 d has been completed.

Once the ultraviolet-ozone treatment 22 a and the RTO process 22 dhavebeen performed, there is an option to provide additional amounts ofoxide 22 g. Further growth 22 k from the consumption of silicon may beused to provide oxide similar to that resulting from the initial growth.Alternatively, an oxide, such as Ta₂O₅ (22 h), could be deposited.Regardless of the precise methods of providing oxides in these steps 22d, 22 a, and 22 g, they are understood to cooperate in achieving a giventhickness of oxide at the end of the oxide formation stage 22. Thus, agreater oxide contribution in one step may relieve the need to producemore oxide in other steps. This “given thickness” of oxide variesdepending on the structures formed, as one skilled in the art canappreciate. Exemplary thicknesses are discussed below.

Achieving this given thickness of oxide is further aided by an optionaladditional cleaning step 22 e, such as a second vapor clean 22 fperformed after an oxidation step and, preferably, interposed betweenoxidation steps such as 22 d and 22 g. As a result of this vapor clean22 f, some or all of the oxide present may be removed. If a gatedielectric such as Ta₂O₅ is deposited, some of the oxide provided in aprior step should remain to act as an adhesion layer between thesubstrate and the gate dielectric. In addition to curing any problemsthat might result from an inadvertent overgrowth of oxide, this secondvapor clean 22 f also serves to remove defects that would otherwiseexist in the finished device. Defective oxides can arise if there arecertain constituents, such as contaminants, in the silicon from whichthe oxide grows. As the silicon is consumed in steps such as 22 d and 22a, the resulting oxide may retain those contaminants. By removing all orpart of this grown oxide, the second vapor clean 22 f also removes thosecontaminants associated with the removed oxide.

While the amount of oxide at the end of this stage 22 may have agenerally constant thickness, such a limitation is not necessary for thepresent invention. In fact, providing for variations in oxide thicknessis actually desired in certain circumstances, such as in providing thetopography needed for embedded DRAM memory devices. FIG. 2 illustrateshow this topography is achieved in the prior art. As seen in FIG. 2 a, athin layer of SiO₂ 30 is grown on the silicon substrate 32. FIG. 2 bindicates that the SiO₂ layer 30 is then covered with a mask layer 34,such as one made of silicon nitride. The mask layer 34 is patterned toexpose an area 36 where further oxide growth is desired. Additionaloxide growth is then carried out in FIG. 2 c, resulting in more siliconbeing consumed in the exposed area 36, while most of the SiO₂ layer 30under the silicon nitride mask 34 retains its original thickness. InFIG. 2 d, the mask 34 and SiO₂ layer 30 are removed, leaving behind abi-level topography for the substrate 32. It is preferred that theresulting levels be parallel, but differences in slopes are allowable tothe extent that the devices would still be functional. Further oxidationand masking steps are carried out to form structures such as the fieldoxide isolation regions 38 and gate oxide regions 40 and 41 depicted inFIG. 2 e. This prior art method, however, depends on the higher levelsof the substrate 32 being relatively free of constituents such ascontaminants. Should the substrate 32 be contaminated in an area underthe mask layer 34, then the gate oxide 40 formed by consuming silicon inthat area will also be contaminated.

At least one embodiment of the current invention is free of suchdependency. FIG. 3 a depicts the unoxidized substrate 32 havingcontaminants 42. Some of these contaminants 42 become part of the grownSiO₂ layer 30 after oxidation, as depicted in FIG. 3 b. The effect ofthe second vapor clean step 22 f, shown in FIG. 1, can be seen in FIG. 3c, wherein the SiO₂ layer 30, along with its associated contaminants 42,is removed. Subsequent oxidation, masking, and removal steps may then betaken to achieve the bi-level topography needed for embedded DRAMdevices. Assuming some contaminants 42 remain in the substrate 32, thesubsequent oxidation and removal steps will preferably eliminate most ifnot all of these contaminants 42.

Moreover, it is not necessary to completely remove the initial SiO₂layer 30, as shown in the embodiment depicted in FIGS. 4 a through 4 e.FIG. 4 a once again shows the substrate 32 with the SiO₂ layer 30 grownon top. FIG. 4 b depicts the in-process wafer after the second vaporclean 22 f, wherein only part of the SiO₂ layer 30 has been removed as aresult of that cleaning. Preferably, this partial oxide removal orsubsequent oxide removals will eliminate most if not all of any existingcontaminants or other undesired constituents within the SiO₂ layer.Assuming an exemplary embedded memory topography is desired, it ispreferred that approximately 40 angstroms of the SiO₂ layer 30 remainafter the second vapor clean 22 f. The mask layer 34 is then providedand patterned to expose the area 36. If desired, further cleaning stepscould be taken to remove more of the exposed SiO₂ layer 30 beforeadditional oxide is grown. Alternatively, one may retain the existingSiO₂ layer and continue to grow more oxide, as demonstrated in FIG. 4 d.Regardless of whether this latest cleaning is performed, it is preferredthat the final thickness of the SiO₂ layer 30 in the exposed area 36 bewithin a range of approximately 70 to 90 angstroms for this exemplaryembedded memory structure. Removing the SiO₂ layer 30 and the mask layer34 reveals the bi-level topography of the wafer of FIG. 4 e. Field oxideregions and gate oxide regions may then be formed by theoxidation/cleaning steps described in the above embodiments or by amethod known in the art.

If an oxynitride layer is desired, then a nitridation step 22 j (seen inFIG. 1) may be performed on the oxide layer. One possible way to carryout this step 22 j involves rapid thermal nitridation (RTN), whereinammonia (Nh₃) is introduced to the wafer environment and heated with asource, such as a halogen lamp, to a temperature generally ranging from850° to 1050° C. As a result of this process, the oxide film is rapidlychanged to an oxynitride film.

Regardless of the particular devices being developed on the wafer, oncethe correct amount of oxide or oxynitride is present, an optionalconditioning step 22 i may be performed. In at least one embodiment,this conditioning step 22 i comprises hardening the oxide in anitridizing ambient, such as NO or N₂O. In other embodiments,particularly those involving high dielectric constant materials such asTa₂O₅, the conditioning step can alternatively include exposure to anambient comprised of Nh₃; dichlorosilane (SiCl₂H₂) and Nh₃; an oxygenenvironment, such as ozone; N₂; Ar; or H₂. This exposure would last forat least ten seconds at preferably five to fifteen atmospheres and at atemperature generally between 500° to 750° C. Another conditioningalternative involves steam oxidation, wherein the dielectric is exposedto a mixture of H₂ and O₂. Those skilled in the art understand that sucha mixture may be generated by using a plasma torch. The currentinvention, however, also includes a conditioning step wherein a plasmatorch is not used; rather, H₂ and O₂ are brought together within theprocess chamber at a pressure of generally one atmosphere or lower andat a temperature generally ranging from 500° to 900° C.

If an embodiment of the current invention is used to provide a gateoxide, one advantage will be to reduce the current leakage of a deviceor, at least, counteract factors that could increase the leakage.Moreover, the cleaning, oxidizing, and conditioning steps describedabove have uses in addition to altering the topography of the siliconsubstrate and to providing some form of gate oxide. These steps, forexample, can be used to form the tunnel oxide 44 of a flash memory cell46 depicted in FIG. 5, as well as the entire oxide 48 for that cell 46.The flash memory cell 46 pictured is more specifically aflash-electrically erasable programmable read only memory (flash-EEPROM)cell formed in a p-type substrate 50 having n-type source and drainregions 52, 54. Over the substrate 50, a floating gate 56 is providedwithin the oxide 48. A control gate 58 is also within oxide 48 and islocated over the floating gate 56. The floating gate 56 is separatedfrom the substrate by the tunnel oxide 44. This tunnel oxide 44 is arelatively thin oxide layer; while it can be as thin as thirty to fortyangstroms, it is preferably closer to seventy to one hundred angstromsthin. The tunnel oxide 44 is so named because memory programming anderasing is accomplished by way of Fowler-Nordheim tunneling through thistunnel oxide 44. Thus, through an embodiment of the current invention,the tunnel oxide 44 could be provided through an initial oxidation stepwith a cleaning to reduce the oxide to a desired thickness.Alternatively, the oxide could be completely cleaned away, allowing asubsequent oxidation step to form the tunnel oxide 44 at a lower levelof the substrate 50. The rest of the oxide 48 could be formed by anadditional oxidation step or by still more oxidation/cleaning cycles.

As another example, these cleaning, oxidizing, and conditioning stepscan be used to provide a gate oxide for devices isolated using a shallowtrench isolation (STI) process. Such a device in-progress appears inFIG. 6, wherein an etched substrate 60 defines trenches 62 thatelectrically isolate one cell site from another. After providing atrench fill 64, the gate oxide 66 is grown in a high-pressure oxidationenvironment using the steps described above. For instance, the gateoxide 66 could be grown at a pressure generally ranging from five tofifteen atmospheres.

Given these varying environments for the oxide, the specific steps takenwithin the stage of forming a structure 24 will depend in part on thecontext in which the oxide is formed—such as whether it is formed for agate in an embedded DRAM or to sculpt the substrate to accommodate sucha gate, for a floating gate in a tunnel oxide, for a gate in an STIcell, or for other structures. many instances, the stage of forming astructure 24 will involve a step of forming a gate 24 a which, in turn,is often formed by depositing a polysilicon film. Moreover, asilicon-germanium film may be provided as an option by doping thepolysilicon film with germanium, wherein the germanium concentration maygenerally range from 2% to 25%. Other alternatives to depositingpolysilicon include depositing tantalum nitride, titanium nitride, andtungsten nitride.

Once the stage of forming a structure 24 has been completed, the wafermay undergo further processing, such as steps taken to form word lines.It should also be noted that, in a preferred embodiment, it is desirableto cluster the steps from the first vapor clean 20 b to the stageinvolving forming a structure 24. Of course, in an even more preferredembodiment, every step would be clustered. This would serve to furtherreduce the constituents such as contaminants that might appear in anoxide as well as other layers.

In general, this documents discusses, among other things, methods forproviding an oxide layer during the processing of a semiconductordevice. One exemplary embodiment relates to a method wherein an oxide isprovided on a substrate surface and is then subjected to a cleaningprocess, followed by a provision of still more oxide. The oxide ineither step could be grown or deposited. Moreover, the cleaning step maybe used to remove all or some of the first provision of oxide. Thisembodiment has the advantage of removing any oxide that may carryconstituents such as contaminants that were part of the underlyingsubstrate. Thus, this embodiment can be used to provide a morecontaminant-free oxide for a semiconductor device. Alternatively, thisembodiment can be used to selectively consume portions of a substrate,thereby allowing memory structures such as embedded memories to beformed within the lower elevations of the substrate.

Another exemplary embodiment allows for providing a gate dielectrichaving a high dielectric constant. Such dielectrics include oxides suchas tantalum pentoxide (Ta₂O₅), or layers produced through rapid thermalnitridation (RTN), such as oxynitrides. In this embodiment, a layer ofoxide or oxynitride serves as an adhesion layer between the substrateand the subsequently deposited Ta₂O₅. A cleaning step between providingthe adhesion layer and providing the Ta₂O₅ layer is optional. Oneadvantage of this embodiment is that leakage current can be improved.

Yet another exemplary embodiment covers a range of steps for processingthe semiconductor device, including a vapor clean, an initial oxidegrowth or deposition, a subsequent oxide growth or deposition, anoptional second vapor clean between the two oxide steps, an oxidehardening, and the formation of an electrode over the second oxide. In amore preferred version of this embodiment, these steps are clustered,wherein transportation between the various processes are performed in acommon controlled environment, such as a nitrogen atmosphere or avacuum. The cluster process environment lowers the amount ofcontaminants having access to the in-process semiconductor device, andthe cleaning steps help to negate the effects of any contaminants thatappear within the device despite the attempts to control theenvironment.

Finally, one skilled in the art can appreciate that, although specificembodiments of this invention have been described above for purposes ofillustration, various modifications may be made without departing fromthe spirit and scope of the invention. For example, providing oxideunder the current invention is not limited to at most two oxidationsteps; any number of oxidation steps and cleaning steps as needed arecovered, as shown by the arrow in FIG. 1 looping from step 22 g back to22 e. Further, any masking steps that might be needed to allow oxidationand cleaning in selected areas are also included. Accordingly, theinvention is not limited except as stated in the claims.

1. A method for forming a semiconductor device, comprising: removing acontaminant from a surface of the semiconductor device; forming a firstoxide over the surface; forming a second oxide over the surface; formingan electrode over the surface; and clustering the removing thecontaminant, the providing the first oxide, the providing the secondoxide, and the providing the electrode over the surface.
 2. The methodof claim 1, wherein providing the first oxide over the surface comprisesgrowing oxide on the surface.
 3. The method of claim 2, wherein growingthe oxide on the surface comprises rapidly thermally oxidizing thesurface.
 4. The method of claim 3, wherein growing the oxide on thesurface comprises inducing chemical oxide growth through anultraviolet-ozone treatment before rapidly thermally oxidizing thesurface.
 5. The method of claim 4, wherein providing the second oxidecomprises depositing the second oxide onto the grown oxide.
 6. Themethod of claim 4, wherein providing the second oxide comprisesproviding an oxide having a composition similar to a composition of thefirst oxide.
 7. A method for processing a semiconductor device,comprising: performing a vapor clean on the semiconductor device;growing a first amount of oxide on the semiconductor device; depositinga second amount of oxide on the semiconductor device; and forming a gateon the second amount of oxide.
 8. The method of claim 7, furthercomprising gettering the first amount of oxide.
 9. The method of claim8, wherein forming the gate comprises depositing polysilicon on thesecond amount of oxide.
 10. The method of claim 9, wherein forming thegate comprises doping the polysilicon with germanium.
 11. The method ofclaim 10, wherein doping the polysilicon with germanium comprisesproviding a germanium concentration generally ranging from 2% to 25%within the polysilicon.
 12. A method for forming a gate for asemiconductor device, comprising: bonding contaminants at a level of thesemiconductor device; providing an adhesion layer at a gate site on thelevel; forming a gate oxide made of tantalum pentoxide over the gatesite; and providing a gate material over the gate oxide.
 13. The methodof claim 12, wherein providing the adhesion layer comprises providing anoxynitride layer over the level.
 14. The method of claim 13, furthercomprising conditioning the gate oxide.
 15. The method of claim 14,wherein conditioning the gate oxide comprises hardening the gate oxide.16. The method of claim 15, wherein conditioning the gate oxidecomprises exposing the gate oxide to a nitridizing ambient.
 17. Themethod of claim 16, wherein providing the gate material comprisesdepositing a material selected from a group of materials comprisingtitanium nitride and tungsten nitride.
 18. The method of claim 14,wherein conditioning the gate oxide comprises performing steam oxidationof the gate oxide.
 19. A method for developing a semiconductor device,comprising: cleaning a level of the semiconductor device; furnishing afirst oxide layer at the level; cleaning the first oxide layer;furnishing a second oxide layer over the level; hardening the secondoxide layer; and furnishing an electrode on the second oxide layer. 20.The method of claim 19, wherein cleaning the level comprises: removing aresidue from the level; and neutralizing a contaminant within the level.21. The method of claim 20, wherein removing the residue comprisespassivating the level.
 22. The method of claim 21, wherein furnishingthe first oxide layer at the level comprises: providing an ozoneenvironment at the level; and irradiating the ozone environment withultraviolet radiation.
 23. The method of claim 22, wherein furnishingthe first oxide layer at the level comprises performing rapid thermaloxidation at the level.